1. Field of the Invention
The present invention relates to information processing systems and semiconductor storage devices, and particularly to a beneficial technology to be applied to a system including a random access memory and an information processing device for controlling the random access memory.
2. Description of Related Art
For example, Japanese Patent Laid-Open No. 2005-235248 describes a semiconductor storage device which aims to reduce the time for a DMA test and to improve the inspection accuracy thereof. Specifically, in this semiconductor storage device, when the test is conducted at a low frequency, the IO terminal functions as an input/output terminal (a common mode), and when the test is conducted at a high frequency, one part of the IO terminal functions as an input terminal and the other part functions as an output terminal (a separate mode). Further, Japanese patent Laid-Open No. 10-50054 describes a semiconductor storage device which aims at the reduction of skew in read data on the side of a memory controller. Specifically, the semiconductor storage device includes an IO common mode and an IO separate mode, in which in the IO separate mode, data is inputted from an address terminal and outputted from an IO terminal. Furthermore, Japanese patent Laid-Open No. 10-64257 describes a semiconductor storage device which enables a high-speed read-modify-write for a 3D computer graphics buffer. Specifically, the semiconductor storage device includes a memory array which allows independent inputting and outputting of data during read/write, a circuit which decodes and outputs an address signal for reading data to the memory array, and a circuit which decodes and outputs a signal which is obtained by delaying the address signal for reading data by a predetermined number of clocks as an address signal for writing data, to the memory array.
Prior to the present application, the inventers of the present invention investigated the operation in an information processing system made up of an information processing device and a random access memory.
There are stored in the random access memory, though not specifically limited to, a communication control program to be processed in the information processing device, and a program and data for processing media such as MPEG, JPEG and graphics. Regarding the communication control program, the information processing device (for example, CPU: Central Processing Unit) reads out a communication control command stored in the random access memory and performs communication control. At this time, reading of commands from the random access memory will frequently take place. On the other hand, regarding the programs for processing media such as MPEG, JPEG and graphics, the information processing device reads the commands and data of these programs stored in the random access memory, processes the data according to a predetermined command in the information processing device, and writes the data into the random access memory. At this time, reading and writing of data from and into the random access memory will frequently take place in an alternate manner.
Therefore, to achieve a high-speed operation of a program for processing media, the data transfer speed while reading and writing data alternately take place is important, and to achieve a high-speed operation of a communication control program, the latency, until a cycle of data read is finished, is important. In a random access memory in which the data signal is configured to be bidirectional, that is, in a random access memory in which the data signal is controlled by a bidirectional buffer, when reading and writing data to and from a random access memory alternately take place at frequent intervals, the time for switching the bidirectional buffer increases thereby inevitably reducing the data transfer speed. That is, in generally known conventional random access memories, it is difficult to realize a high-speed data transfer and a low latency by flexibly coping with the program being executed in the information processing device.
Under such circumstances, the above described Japanese Patent Laid-Open No. 2005-235248 and Japanese patent Laid-Open No. 10-50054 describe a semiconductor storage device which aims at the reduction of testing time and read-data skew. However, since those devices have configurations specialized for desired objects, they are not configured to improve the efficiency of the program processing as described above. Further, although using the semiconductor storage device of Japanese Patent Laid-Open No. 10-64257 will make it possible to effectively realize a read-modify-write for the same address, it is difficult to flexibly improve the efficiency depending on various program processing as described above.